The International Technology Roadmap for Semiconductors predicts memories to occupy more than 90% of the chip silicon area in the foreseeable future. Due to their ultra large scale of integration and vastly complex structures, memory arrays are far more vulnerable to defects than the remaining parts of integrated circuits. Embedded memories have already started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in test procedures. Many types of failures, often not seen earlier, originate in the highest density areas of semiconductor devices where diffusions, polysilicon, metallization, and fabricated structures are in extremely tight proximity to each other. Failing to properly test all architectural features of the embedded memories can eventually deteriorate the quality of test, and ultimately hinder yield.
Embedded memories are clearly more challenging to test and diagnose than their stand-alone counterparts. This is because their complex structures are paired with a reduced bandwidth of test channels resulting in limited accessibility and controllability. Consequently, the memory built-in self-test (MBIST) has quickly established itself as one of the mainstream design for test (DFT) methodologies as it allows one to generate, compress, and store on chip very regular test patterns and expected responses by using a relatively simple test logic. The available input/output channels, moreover, suffice to control BIST operations, including at-speed testing and detection of time-related faults.
Non-volatile memories are among the oldest programmable devices, but continue to have many critical uses. ROM, PROM, EPROM, EEPROM, and flash memories have proved to be very useful in a variety of applications. Traditionally, they were primarily used for long term data storage, such as look-up tables in multi-media processors or permanent code storage in microprocessors. Due to the high area density and new submicron technologies involving multiple metal layers, ROMs have also gained popularity as a storage solution for low-voltage/low-power designs. Moreover, different methods such as selective pre-charging, minimization of non-zero items, row(s) inversion, sign magnitude encoding, and difference encoding are being employed to reduce the capacitance and/or the switching activity of bit and word lines. Such design, technology, and process changes have resulted in an increase in the number of ROM instances usually seen in a design. New non-volatile memories such as ferroelectric, magnetoresistive, and phase changed RAMs retain data when powered off but are not restricted in the number of operation cycles. They may soon replace other forms of non-volatile memory as their advantages, e.g., reduced standby power and improved density, are tremendous.
It has become imperative to deploy effective means for testing and diagnosing non-volatile memory failures. No longer is it sufficient to determine whether such a memory failed or not. In defect analysis and fine-tuning of a fabrication process, the ability to diagnose the cause of failure is of paramount importance. In particular, new defect types need to be accurately identified and well understood. It is also a common desire to verify if the programming device that is writing the ROM is working correctly. The method and accuracy of the diagnostic technique, therefore, is a critical factor in identifying failing sites of a memory array. It can be performed either on chip or off-line after downloading compressed test results.